As complimentary metal-oxide semiconductor (CMOS) device dimensions are scaled down, borderless contacts become necessary in order to fulfill the stringent design rule and to provide wider process margins to accommodate the misalignment during contact masking. For borderless contact schemes, a layer of dielectric film is needed to function as an etch stop layer (ESL). This etch-stop layer protects the shallow-trench-isolation (STI) oxide during the contact-hole anisotropic plasma-etching process. Prevention of excessive STI oxide loss is crucial in order to minimize current leakage through the active-isolation region.
Current borderless contact practices use silicon nitride (SiN) and/or silicon oxynitride (SiON) as the ESL. Current dual damascene fabrication practices use SiN and/or SiCO, SiCN or SIC as the etch stop layer/barrier layer.
Etch selectivity remains an issue for both of these current practices as these materials are silicon-based and standard etch chemistry would be challenging for advanced aspect-ratio etching.
U.S. Pat. No. 6,274,517 B1 to Hsia describes a method of fabricating a PNO (phoslon) spacer.
U.S. Pat. No. 6,194,762 B1 to Yamazaki et al. describes a borderless process using SiN as the etch stop layer.
U.S. Pat. No. 6,072,237 to Jang et al. describes a method for forming a borderless contact structure with a SiN etch stop layer.
U.S. Pat. No. 5,384,281 to Kenney et al. describes a process for etching narrow features, particularly submicron borderless contacts using an SiN etch stop layer.
U.S. Pat. No. 6,239,026 B1 to Liu et al. describes reducing poisoned vias in submicron process technology by reducing the occurrence of over-etched vias through the inclusion of an etch stop layer.
U.S. Pat. No. 4,172,158 to Li describes a method of forming an amorphous phosphorus-nitrogen-oxygen (PNO or phoslon) material.